The present application relates generally to semiconductor devices, and more specifically to vertical field effect transistors (VFETs) and their methods of production.
The vertical fin field effect transistor structure can be used to form a wide variety of devices, including radio frequency (RF) devices. Vertical fin FETs are devices where the source-drain current flows from a source region to a drain region through a channel region of a semiconductor fin in a direction normal to a substrate surface. An advantage of the vertical FET is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. In vertical fin field effect transistor (FinFET) devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
Aggressive scaling of semiconductor devices, including complementary metal oxide semiconductor (CMOS) devices, and the attendant decrease in critical dimension (CD) may result in increased resistance between conductive elements, including the gate contacts, due to a decreased contact area between conductive regions and the resistivity of the individual conductive layers. In particular, with critical dimension (CD) scaling decreases below the 55 nm node, it has been demonstrated that the cut-off frequency (Fe) in RF devices increases while the maximum achievable frequency (Fmax) disadvantageously decreases.